Contents I. Introduction
Logarithmic and exponential functions, having a wide application in communication and signal processing, are generally implemented using bipolar junction transistors (BJTs) or MOS transistor in weak inversion using their exponential characteristics [5]–[9]. In this paper, a thorough understanding of a mathematical model combined with hardware compatibility has been exploited to realize logarithmic and exponential functions for various analog signals, which leads to an improved design. A low-cost, high-speed architecture for binary logarithm approximation has been proposed by many researchers. Mitchell’s method with a correction stage composed of piecewise linear interpolation and a lookup-table correction is used to compute binary logarithm in [8]. Hardware implementation of log() and antilog() is proposed in [26]. Both the architectures are implemented in an FPGA. Voltage–current relationship of a p-n junction diode and Taylor’s series expansion have been used to realize logarithmic and exponential function [2]–[10]. Significant efforts have been invested in using MOS transistors in saturation region for the implementation of exponential functions [6], [7]. Liu and Liu [5] proposed a compact, low-power, CMOS exponential function generator with a wide dynamic range. A CMOS pseudoexponential function circuit based on Taylor series approximation using MOS transistor operating at saturation region is presented in [6]. Chang and Liu [7] proposed a voltage-mode and a current-mode pseudoexponential function circuit. In [3], a low-voltage CMOS current mode exponential circuit has been described using MOS transistors in weak inversion. Translinear principle is used to implement the approximation to cancel the temperature effect. Maundy et al. [9] introduced a pseudoexponential and pseudologarithmic circuit using operational amplifier (op-amp). Implementation of pseudologarithmic circuit using Taylor’s series expansion has been described in [10].
