Contents I. Introduction
Today's technology uses heavily Digital Signal Processing (DSP) on its applications, and since the past 20 years [1] these applications have been growing up because the performed improvements to digital integrated circuits in speed, integration capabilities and power consumption. The increased speed of integrated circuits allows real time processing of signals with higher bandwidths such as the ones used in communication systems [1]. Nowadays there are Digital Signal Processors (DSPs) devices specifically designed for DSP that perform real time filtering, Fourier transforms, Wavelet transforms, or encoding processes on audio and video signals. Nevertheless, the parallel nature of DSP algorithms has motivated research interest to hardware solutions based on reconfigurable targets such as the Field Programmable Gate Arrays (FPGAs); these solutions have demonstrated improvements in speed and power consumption compared with the DSPs-based ones [2]. There are several FPGA-based DSP solutions, which are developed by private corporations such as Altera and Xilinx. These solutions include FIR filtering cores [3] [4], FFT cores [5] [6], among others; however these cores have expensive licenses for commercial use or they can be used for free only for academic purposes. Nonetheless, a new open source hardware development model inspired from open source software models has been deployed since the last ten years. This model has been supported by communities like OpenCores, which develops open source hardware under the Lesser General Public License (LGPL). OpenCores community has remarkable products as the OpenRISC processor core [7] and the Wishbone bus specification [8], which jointly allow the development of SoC hardware. However, OpenCores community lacks of fully parameterizable DSP cores compatible with the Wishbone bus. By considering previous ideas, we developed cores FIR filter, IIR filter and FFT under the LGPL license, which are compatible with the Wishbone bus and allow the development of DSP-SoC based on the OpenRISC processor [9]. The FIR-filter core is based on the transpose architecture [1] [2], the IIR core is based on the SOS architecture [1] [2], and the FFT core is based on the SDF architecture [10]. The three cores were described using generic and structural VHDL and targeted to an Altera FPGA device. This paper is organized as follows: First, section II describes some theoretical concepts about DSP and Wishbone bus, then section III presents the design of the DSP cores architecture and describes the functional blocks, later the section IV shows the in-system hardware verification results, and finally the conclusion and the acknowledgements are presented.
