Design and characterization of a 10bit pipeline- ADC for 100MSps in 0.18μm CMOS | IEEE Conference Publication | IEEE Xplore

Design and characterization of a 10bit pipeline- ADC for 100MSps in 0.18μm CMOS


Abstract:

Within this work the complete design and characterization of a 10bit Analog to Digital Converter (ADC) for a sample rate up to 100MSps is presented. Therefore pipeline ar...Show More

Abstract:

Within this work the complete design and characterization of a 10bit Analog to Digital Converter (ADC) for a sample rate up to 100MSps is presented. Therefore pipeline architecture with a series of 1.5bit stages has been realized. Each stage contains a sub-ADC (two high speed comparators and a latch) and a multiplying DAC (switched capacitor feedback circuit with a high gain folded cascode operational amplifier plus one analog multiplexer acting as sub-DAC. The fully differential ADC design features a differential input voltage range Vin=±1V, date latency Δ=5cycles supply voltage Vdd=1.8V and a total power dissipation of P~100mW. Comprehensive characterization using both, direct sampling with a discrete measurement setup as well as a smart setup using a high-speed FPGA board was done: For a sample rate of fsample=10MHz/100MHz an ENOB=8.55/6.35bit, SINAD=59.4/46.3dB, THD=-57.2/-44.3dB, SNDR=53.2/40.0dB together with a standard deviation of INL σINL=1.4/10.7bit and DNL σDNL=0.19/0.6bit could be achieved. The entire ADC chip measures A=2mm × 2mm and was realized in a lP6M (HighRes poly and Cmim) 0.18μm CMOS technology.
Date of Conference: 09-09 October 2014
Date Added to IEEE Xplore: 06 November 2014
ISBN Information:
Conference Location: Graz, Austria

I. Introduction

Analog to digital converters (ADCs) are omnipresent in communications, imaging and instrumentation systems. Among these ADCs, the pipelined architecture presents the best trade-off between high conversion rate, resolution and power consumption. Since the introduction of the pipelined ADC a lot of research efforts aim to improve its performance [1]. The accuracy of the residue generated by a multiplying DAC (MDAC) depends on the settling accuracy of the operational amplifier (op-amp) and the capacitor matching in the reconstruction DAC. The power consumed in wideband opamps often limits the total ADC power, especially when high linearity and resolution requirements have to be met. One approach to reduce the power consumption is to use an open-loop amplifier for residual amplification. The linearity of this residue amplifier has to be enhanced by additional digital error calibration [2].

References

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