I. Introduction
Analog to digital converters (ADCs) are omnipresent in communications, imaging and instrumentation systems. Among these ADCs, the pipelined architecture presents the best trade-off between high conversion rate, resolution and power consumption. Since the introduction of the pipelined ADC a lot of research efforts aim to improve its performance [1]. The accuracy of the residue generated by a multiplying DAC (MDAC) depends on the settling accuracy of the operational amplifier (op-amp) and the capacitor matching in the reconstruction DAC. The power consumed in wideband opamps often limits the total ADC power, especially when high linearity and resolution requirements have to be met. One approach to reduce the power consumption is to use an open-loop amplifier for residual amplification. The linearity of this residue amplifier has to be enhanced by additional digital error calibration [2].