An effective conductance cancellation method with minimal design effort

An easy-to-implement conductance cancellation method is proposed. To be specific, the only design work involved in the proposed method is to size a transistor in the negative conductance of the NMOS side. In addition, without the aid of any tuning or calibration circuit and under all process corners, the method is able to maintain a DC gain enhancement of over 28.9dB under temperatures between -40 and 80°C, of over 27.6dB under supply voltage between 1.4V and 2V, and of over 29dB under differential output swing between -1.1V and 1.1V. Furthermore, the power and area overhead of the method are respectively only 7% and 3% of those of conventional op amps.

I. Introduction

Achieving a high DC gain for op amps is fundamental to many high precision analog and mixed signal circuits such as sigma-delta converters and switched-capacitor circuits. But as feature sizes of transistors continuously scale down and supply voltage decreases, the intrinsic gains of the transistors are diminishing. In an effort to enhance DC gain of an op amp, four methods have been reported: a) cascoding multiple transistors in a stack; b) cascading multiple gain stages; c) gain-boosting; and d) conductance cancellation. However, all these methods have shortcomings.