An asynchronous finite impulse response filter design for Digital Signal Processing circuit

The clockless feature of asynchronous circuit promotes its application in Digital Signal Processing (DSP) under special applications such as ultra-low power and extreme environments. In this paper, Finite Impulse Response (FIR) filter is implemented in delay-insensitivity asynchronous circuit using the pipeline architecture of Multi-Threshold NULL Conventional Logic (MTNCL). The computing units with different pipeline stages and pattern delay shift registers are integrated as 4 designs of FIR filter using the IBM 130nm 8RF process. Simulation results demonstrate the tradeoff between system throughput and energy efficiency, as the number of pipeline stage changes in the circuit.

I. Introduction

With the trend of integrating complex systems on a single chip (SoC) for battery-powered remote computing and communication, low power circuit design is essential for the success of scientific exploration under extreme environments. Comparing with its synchronous counterpart, asynchronous circuit design exhibits interesting properties besides energy efficiency, such as electromagnetic interference reduction [1], immunity to metastable behavior [2] and ultra-wide temperature operations [3]. One promising application of the asynchronous paradigm is Digital Signal Processing (DSP) system, which contains three parts in a classical structure: A/D converters (ADC), digital processing circuits and D/A converters. Previous research [4], [5] indicates asynchronous ADC with irregular “level-crossing” sampling scheme is energy efficient to take advantage of signals with statistical properties. Although the irregular front-end stream can be converted into a clock sampled stream for standard signal processing, the natural way of using asynchronous ADC is combining irregular sampling and asynchronous digital processors in a fully asynchronous system.