Electrical and physical analysis of a 28nm FPGA programmable delay circuit single tap delay failure

This failure analysis is based on a 28nm FPGA IDelay logic block which features an all programmable, 32-tap delay line. Each tap delay is carefully calibrated to provide an absolute delay value of 78ps independent of process voltage, and temperature variations. To locate the failing IDelay site, scan chain methodology was utilized. Combinations of delay tests were created to localize the defect within the IDelay block and the failure was isolated to a single tap delay circuit. Photon emission analysis validated the electrical analysis with an emission successfully detected at the suspect area. Physical failure analysis utilizing a combination of AFP current contrast imaging and nano-probing analysis at the contact layer further isolated the area of interest to a specific transistor. Die delayering and SEM high beam inspection did not show any anomalies, but subsequent TEM analysis revealed diffusion bridging at the failure location.

I. Introduction

This case study is of a 28nm field-programmable gate array (FPGA) device. The device had exhibited basic functional failure during ATE testing. An input delay (IDELAY) pattern failure was identified based on the ATE result.