Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

I. Introduction

Today’s multicore chip architectures require no trivial test solutions imposed by the relentless miniaturization of semiconductor devices, which have become much faster and less power hungry than their predecessors. This trend has given rise to the growing popularity of system-on-chip (SoC) designs because of their ability to encapsulate many disparate types of complex IP cores running at different clock rates with different power requirements and multiple power-supply voltage levels. Many SoC-based test schemes proposed so far utilize dedicated instrumentation, including test access mechanisms (TAMs) and test wrappers [7], [9], [22]. TAMs are typically used to transfer test data between the SoC pins and embedded cores, whereas test wrappers form the interface between the core and SoC environment. Solutions involving both TAMs and wrappers accomplish such tasks as optimizing test interface architecture [26] or control logic [20] while addressing routing and layout constraints or hierarchy of cores [2], [5], scheduling test procedures [1], [18], [19], [21], [31], and minimizing power consumption [8], [16], [30]. Techniques proposed in [4], [9], [10], and [25] attempt to minimize SoC test time. The integrated scheme of [9] reduces the test time by optimizing dedicated TAMs and pin-count-aware test scheduling. Packet-switched networks-on-chip [25] can replace dedicated TAMs in testing of SoC by delivering test data through an on-chip communication infrastructure.