FPGA based phase detector for high-speed clocks with pico-seconds resolution

Many applications require some type of phase detectors to determine the phase relation between synchronous clocks. The European XFEL timing system [1],[2],[3] utilizes numerous phase detectors to monitor and keep clocks and triggers phase stable.Modern digital systems are often based on FPGAs. These FPGAs could be used as phase detectors as well, with proper design considerations for the hardware and firmware. An FPGA based phase detector has therefore been developed that by undersampling the clocks can measure the relative phase with great accuracy. This work presents the principles of an FPGA based phase detector, describes the numerous challenges involved, discusses the benefits but also some of its limitations, and finally some measurement results are shown.

I. Introduction

IN many applications discrete phase detectors circuits are used to measure phases between different synchronous, usually high-speed, clocks. These phase detector circuits often output analog voltages that also require ADCs to be implemented in the system, adding more complexity and cost to the design. If a system also contains an FPGA with many available IIOs it would be desirable to use the FPGA as a phase detector for a cost efficient solution with simpler PCB design.