A 20-ps Time-to-Digital Converter (TDC) Implemented in Field-Programmable Gate Array (FPGA) with Automatic Temperature Correction

This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain. Accordingly, a simplified temperature correction scheme by using a dedicated correction channel to measure the coefficient and correct fine time result for all TDC channels is implemented and tested. This method shows only few picosecond errors for both simulation and measurement. With this correction approach, a TDC precision of 21 ps has been achieved in Cyclone II FPGA under a wide ambient temperature range from 0°C to 60°C. Several design key points are also described in this paper.

I. Introduction

C ARRY chain structure in a field-programmable gate array (FPGA) can be used as the delay chain in time-to-digital converter for its intrinsic time resolution of tens of picoseconds. Benefiting from carry chain structure, multi-channel time-to-digital converters (TDCs) with very high precision have been implemented in single chip [1]–[7]. However, the delay time of carry chain is very sensitive to power supply voltage and temperature, thus the measurement precision could significantly deteriorate due to voltage and temperature (VT) variation [4], [5], [7].