Equivalence Checking between SLM and TLM Using Coverage Directed Simulation

The always increasing complexity of digital system makes designers start the design from more abstract System Level Modeling (SLM). However, the SLM arouses a new challenge for verification engineer to guarantee the functional equivalence between SLM specifications and Transaction Level Modeling (TLM) or other lower level implementations. This paper proposes a novel method for equivalence checking between SLM and TLM based on coverage directed simulation. In the proposed method, firstly quality measurements based on both code and functional coverage are used to generate simulation stimuli for SLM. Then the generated stimuli are used to simulate the SLM and TLM designs concurrently. Finally, equivalence checking is carried out based on the simulation results of the selected observing variables. With the proposed method, we can check the equivalence between SLM and TLM designs more efficiently with less simulation cost. The promising experimental results show the efficiency of our method.

I. Introduction

As system-on-a-chip (SoC) designs complexity increase, designers shift toward System Level Modeling (SLM) by facilitating more abstract design description (e.g., with C++ or SystemC) to generate low level descriptions (e.g., RTL models) automatically. The increasing complexity makes verification of SoC designs extremely hard. To guarantee the correctness of models of all the levels, designers have to verify each level of the design thoroughly. Equivalence checking techniques provide a promising solution to fill the gap between the different levels of design and reuse the effort of high-level verification.