Abstract:
The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first ...Show MoreMetadata
Abstract:
The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO/sub 2/ at expected operating voltages. The results of SiO/sub 2//alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO/sub 2/ thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO/sub 2/ on the current characteristics of the dielectric stack increases.
Published in: IEEE Transactions on Electron Devices ( Volume: 45, Issue: 6, June 1998)
DOI: 10.1109/16.678572
Citations are not available for this document.
Cites in Patents (7)Patent Links Provided by 1790 Analytics
1.
Govoreanu, Bogdan; Rosmeulen, Maarten; Blomme, Pieter, "NON VOLATILE MEMORY DEVICES"
Inventors:
Govoreanu, Bogdan; Rosmeulen, Maarten; Blomme, Pieter
Abstract:
Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.
Assignee:
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
Filing Date:
02 March 2006
Grant Date:
19 February 2008
Patent Classes:
Current U.S. Class:
257321000, 257324000, 257E21210, 257E29304, 257E29309
Current International Class:
H01L0297880
2.
Setton, Michael, "ULSI MOS WITH HIGH DIELECTRIC CONSTANT GATE INSULATOR"
Inventors:
Setton, Michael
Abstract:
MOS transistor formed on a semiconductor substrate of a first conductivity type and method of fabrication are provided. The device includes (a) an interfacial layer formed on the substrate; (b) a high dielectric constant layer covering the interfacial layer that comprises a material that is selected from the group consisting of Ta 2 O 5 , Ta 2 (O 1-x N x ) 5 wherein x ranges from greater than 0 to 0.6, a solid solution of (Ta 2 O 5 ) r --(TiO 2 ) 1-r wherein r ranges from about 0.9 to less than 1, a solid solution (Ta 2 O 5 ) s --(Al 2 O 3 ) 1-s wherein s ranges from 0.9 to less than 1, a solid solution of (Ta 2 O 5 ) t --(ZrO 2 ) 1-t wherein t ranges from about 0.9 to less than 1, a solid solution of (Ta 2 O 5 ) u --(HfO 2 ) 1-u wherein u ranges from about 0.9 to less than 1, and mixtures thereof wherein the interfacial layer separates the high dielectric constant layer from the substrate; (b) a gate electrode having a width of less than 0.3 micron covering the high dielectric constant layer; (d) first and second lightly doped regions of a second conductivity type disposed on respective areas of the substrate surface; (e) a source and drain regions of the second conductivity type; and (f) a pair of spacers formed adjacent to the gate electrode and formed on the high dielectric constant layer. The high dielectric layer can be subject to densification. The gate oxide material will significantly improve the performance of an MOS device by reducing or eliminating the current leakage associated with prior art devices.
Assignee:
LAM RESEARCH CORP
Filing Date:
21 July 2003
Grant Date:
09 May 2006
Patent Classes:
Current U.S. Class:
257295000, 257324000, 257411000, 257412000, 257E21165, 257E29152
Current International Class:
H01L0297600, H01L0297920, H01L0212850
3.
Blomme, Pieter; Govoreanu, Bogdan; Rosmeulen, Maarten, "INSULATING BARRIER NVM BANDGAP DESIGN"
Inventors:
Blomme, Pieter; Govoreanu, Bogdan; Rosmeulen, Maarten
Abstract:
An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
Assignee:
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC VZW)
Filing Date:
28 June 2004
Grant Date:
11 April 2006
Patent Classes:
Current U.S. Class:
257321000, 257324000, 257325000, 257E21209, 257E29304
Current International Class:
H01L0297920
4.
Blomme, Pieter; Govoreanu, Bogdan; Rosmeulen, Maarten, "INSULATING BARRIER NVM BANDGAP DESIGN"
Inventors:
Blomme, Pieter; Govoreanu, Bogdan; Rosmeulen, Maarten
Abstract:
An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
Assignee:
INTERUNIVERSITAIR MICOROELEKTRONICA CENTRUM (IMEC VZW)
Filing Date:
25 April 2002
Grant Date:
31 August 2004
Patent Classes:
Current U.S. Class:
257321000, 257314000, 257315000, 257324000, 257637000, 257638000, 257E21209, 257E29304, 438263000, 438464000, 438594000
Current International Class:
H01L0297880000
5.
Setton, Michael, "ULSI MOS WITH HIGH DIELECTRIC CONSTANT GATE INSULATOR"
Inventors:
Setton, Michael
Abstract:
MOS transistor formed on a semiconductor substrate of a first conductivity type and method of fabrication are provided. The device includes (a) an interfacial layer formed on the substrate; (b) a high dielectric constant layer covering the interfacial layer that comprises a material that is selected from the group consisting of Ta 2 O 5 , Ta 2 (O 1-x N x ) 5 wherein x ranges from greater than 0 to 0.6, a solid solution of (Ta 2 O 5 ) r -(TiO 2 ) 1-r wherein r ranges from about 0.9 to 1, a solid solution (Ta 2 O 5 ) s -(Al 2 O 3 ) 1-s wherein s ranges from 0.9 to 1, a solid solution of (Ta 2 O 5 ) t -(ZrO 2 ) 1-t wherein t ranges from about 0.9 to 1, a solid solution of (Ta 2 O 5 ) u -(HfO 2 ) 1-u wherein u ranges from about 0.9 to 1, and mixtures thereof wherein the interfacial layer separates the high dielectric constant layer from the substrate; (b) a gate electrode having a width of less than 0.3 micron covering the high dielectric constant layer; (d) first and second lightly doped regions of a second conductivity type disposed on respective areas of the substrate surface; (e) a source and drain regions of the second conductivity type; and (f) a pair of spacers formed adjacent to the gate electrode and formed on the high dielectric constant layer. The high dielectric layer can be subject to densification. The gate oxide material will significantly improve the performance of an MOS device by reducing or eliminating the current leakage associated with prior art devices.
Assignee:
LAM RESEARCH CORP
Filing Date:
30 June 1998
Grant Date:
27 April 2004
Patent Classes:
Current U.S. Class:
438287000, 257E29152
Current International Class:
H01L0213360000
6.
Blomme, Pieter; Govoreanu, Bogdan; Rosmeulen, Maarten, "Insulating barrier for non-volatile memory device"
Inventors:
Blomme, Pieter; Govoreanu, Bogdan; Rosmeulen, Maarten
Abstract:
An insulating barrier (20) extending between a first conductive region (21) and a second conductive region (25), the insulating barrier (20) being provided for tunnelling charge carriers from the first (21) to the second region (25), the insulating barrier (20) comprising a first portion (22) contacting the first region (21) and a second portion (23) contacting the first portion (22) and extending towards the second region (25), the first portion (22) being substantially thinner than the second portion (23), the first portion (22) being constructed in a first dielectric and the second portion (23) being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
Assignee:
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
Filing Date:
19 October 2001
Grant Date:
30 October 2002
Patent Classes:
Current International Class:
H01L0212800000, H01L0295100000, H01L0297880000
7.
Ahmed, Khaled Z.; Bui, Nguyen D.; Ibok, Effiong; Hauser, John R., "MOSFET TEST STRUCTURE FOR CAPACITANCE VOLTAGE MEASUREMENTS"
Inventors:
Ahmed, Khaled Z.; Bui, Nguyen D.; Ibok, Effiong; Hauser, John R.
Abstract:
An apparatus and method used in extracting polysilicon gate doping from C-V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 .mu.m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.
Assignee:
ADVANCED MICRO DEVICES INC
Filing Date:
05 June 2000
Grant Date:
29 October 2002
Patent Classes:
Current U.S. Class:
438014000, 257288000, 324500000, 324762090, 438018000, 438197000
Current International Class:
G01R0312600000, H01L0216600000
