An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space

This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-$\mu\hbox {m}$ CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of $\pm$1.5 LSB, a power consumption of 328.8 $\mu\hbox {W}$, and a die area of 0.28 $\hbox {mm}^{2}$.

I. Introduction

AS AN electronic circuit block can convert time information to digital information, the use of time-to-digital converters (TDCs) has increased. In particular, the TDC performance has increased with technology scaling because the TDC can be constructed using all-digital blocks.