Impact of Fermi Level Pinning Due to Interface Traps Inside the Conduction Band on the Inversion-Layer Mobility in $\hbox{In}_{x}\hbox{Ga}_{1 - x}\hbox{As}$ Metal–Oxide–Semiconductor Field Effect Transistors

We have quantitatively evaluated the interface trap density inside the conduction band (CB) of $\hbox{In}_{x}\hbox{Ga}_{1 - x}\hbox{As}$ metal–oxide–semiconductor (MOS) structures and have systematically investigated the impact of the interface traps inside the CB on the inversion-layer mobility in $\hbox{In}_{x} \hbox{Ga}_{1 - x}\hbox{As}$ MOS field-effect transistors with various interface structures. Furthermore, we have tried to clarify the physical origin of the interface traps inside the CB. It was found that a large number of interface traps are distributed inside the CB of $\hbox{In}_{x} \hbox{Ga}_{1 - x}\hbox{As}$ inducing Fermi level pinning (FLP), the energy level of which is tunable by changing the $\hbox{In}_{x}\hbox{Ga}_{1 - x}\hbox{As}$ MOS interface structures. Furthermore, it was clarified that FLP inside the CB degrades the mobility in the high inversion carrier concentration region. We also found from the obtained results and reported theoretical results that a possible physical origin of the interface traps inside the CB is As–As dimers formed at the interfaces.

I. Introduction

is a candidate material for use in n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) as future complementary MOS devices because of the high electron mobility and light electron effective mass [1]–[3]. Recently, the high performance of MOSFETs with gate insulator films formed using atomic layer deposition (ALD) has been reported in the low inversion carrier concentration region [4]–[6]. However, the reported mobilities in the high region are not in good agreement with those expected based on the difference between the bulk mobilities of Si and InGaAs. Although the physical origins of these insufficient mobilities are not fully understood yet, one possible origin is the large number of interface traps and/or slow traps inside the conduction band (CB) of InGaAs [7]–[14]. It is difficult to determine whether the traps inside the CB reported in Refs. [7]–[13] are interface traps or slow traps. This is because the traps have a continuous distribution from the interface between the InGaAs and the insulator film to the inside of the insulator, and the interactions of free carriers with interface traps and slow traps in – measurements are mixed. Therefore, in the beginning of this paper, the traps are referred to as interface traps. Then, we will discuss which traps are dominant. The existence of interface traps inside the CB has been suggested on the basis of – analyses combined with theoretical calculations for InGaAs MOSFETs and MOS capacitors [7]–[9], while the interface trap density distribution inside the CB has not been directly evaluated without combining theoretical calculations. This means that the validity and accuracy of the evaluation methods for the distribution have not yet been confirmed.