Contents I Introduction
Device variability has drawn lots of attention in advanced technologies. Accurate and appropriate variation modeling has become one of the critical issues for design enablement [1],[2]. The detailed partition for different types of variation sources have been discussed and modeled, including local variation, global variation and variation correlation [3],[4]. Traditionally, circuit designers use the corner model to define the worst-case design envelope. However, there are two major shortages for the corner simulation approach. Firstly, although the worst-case of MOSFETs defined at 3 sigma of the saturation current (Idsat) may fulfill the digital applications, it fails to predict the worst-case condition for analog designs, which are more sensitive to transconductance (Gm) and output conductance (Gds), as shown in Fig. 1. The silicon data show the group of Idsat <italic>/Vtgm</italic> worst case (the solid dots linked by solid line) is not the worst case of (the open dots linked by dash line). A universal corner to cover the device variation is not existed. Under this case, the digital corner defined by Idsat/Vtgm underestimated the variation of Gds.
