A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS | IEEE Journals & Magazine | IEEE Xplore

A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS


Abstract:

A 1-GHz Razor FIR accelerator is implemented in a 65-nm CMOS process. Timing-error detection is implemented using Razor latches on critical paths. Real-time DSP systems n...Show More

Abstract:

A 1-GHz Razor FIR accelerator is implemented in a 65-nm CMOS process. Timing-error detection is implemented using Razor latches on critical paths. Real-time DSP systems necessitate fixed-latency error-correction, which is achieved using a combination of two distinct mechanisms. First, marginal timing violations are corrected using a time-borrow tracking algorithm that uses timing-error detection information to track excessive time borrowing. Second, persistent unresolved time borrowing is corrected at the end of the pipeline using a low-overhead approximate error-correction stage which is based on interpolation. Measurements at peak throughput of over 1 GS/s demonstrate an energy-efficiency improvement of 37%, while maintaining 10% supply voltage margin.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 49, Issue: 1, January 2014)
Page(s): 84 - 94
Date of Publication: 17 October 2013

ISSN Information:


I. Introduction

Sustained scaling of semiconductor process technology, coupled with leakage-limited supply voltage scaling, has led to transistors continuing to become cheaper, while energy budgets come under ever increasing pressure [1]. In light of this, the use of datapath accelerators is increasingly favorable, since specialized hardware is the most efficient use of surplus silicon area in an energy-constrained application. A wide range of power- and performance-sensitive applications have been demonstrated to benefit from custom accelerator blocks, such as network processors [2], smartphone processors [3], [4], and sensor nodes [5], [6]. This trend is particularly apparent in digital signal-processing (DSP) applications, where the unrelenting demands of wireless and multimedia workloads often necessitate specialized datapath hardware. Dedicated accelerator blocks can be specifically optimized and thus typically achieve significantly higher energy efficiency compared with software-only solutions. This comes at the cost of increased development time and limited flexibility.

References

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