High-Performance InAs-On-Insulator n-MOSFETs With Ni-InGaAs S/D Realized by Contact Resistance Reduction Technology

We have systematically analyzed the components of source/drain (S/D) resistance (RSD) in InGaAs n-MOSFETs with Ni-InGaAs metal S/D. It is found that Ni-InGaAs has a low resistivity of ~250 μΩ·cm in a thickness of Ni-InGaAs (T_Ni-InGaAs) of down to ~4 nm. Contact resistance between the contact pads and Ni-InGaAs (R_C) is found to be the most dominant component of R_SD in control InGaAs MOSFETs, because of the existence of Ni oxides. By developing a surface cleaning process using NH₄OH and H₂ plasma for Ni-InGaAs surfaces, we have reduced R_C down to 11 Ω·μm without any accompanying drawbacks. Also, the increase in the channel indium (In) content has provided further R_SD reduction. Employing these R_SD reduction technologies, we present 20-nm-channel length (L_ch) InAs-on-insulator n-MOSFETs on Si substrates with Ni-InGaAs metal S/D. The devices provide a high maximum ON-current (ION) and maximum transconductance (G_m) of 2.38 mA/μm and 1.95 mS/μm at drain voltage (V_D) of 0.5 V. This high performance is attributable to the low R_SD realized by the surface cleaning process of Ni-InGaAs surfaces before the contact pad formation as well as the increase in the In content in the channel layer. Furthermore, it is found that the interface resistance (R_interface) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Ω·μm by increasing the In content in the channel layers.

I. Introduction

III–V compound semiconductors have been seriously considered as new channel materials for future extremely scaled complementary metal-oxide-semiconductor (CMOS) transistors to replace current Si CMOS, because of the expected high injection velocity [1]–[22]. The recent version of the International Technology Roadmap for Semiconductors (ITRS) has suggested that the III–V channels will possibly be introduced in the CMOS technology of the 15-nm node generation and beyond [23].