Protecting FPGA bitstreams using authenticated encryption

This paper describes low cost solution for bitstream security by adding authentication and encryption to the reconfiguration process using Authenticated Encryption (AE). Compact ASIC architecture for AE is presented: Counter with Cipher Block Chaining-Message Authentication Code (CCM). Proposed architecture utilizes Advanced Encryption Standard (AES) in Counter mode (CTR) for encryption. For authentication, AES in Cipher Block Chaining (CBC) is used. Therefore, one architecture of AES for both encryption and authentication decreases the consumed area. In addition, using AES in 32-bit enhances the compact architecture. Our design was evaluated by using a 90 nm CMOS standard cell library. The proposed architecture of CCM requires 0.045 mm². In term of speed, CCM works with 407 Mbps. Our proposed architecture can be used efficiently for secure configuration of FPGAs.

I. Introduction

FPGAs are now being used in consumer products where attacking is more common. In order to redefine their functionality, a bitstream configuration file is sent to the FPGA, this is known as a reconfiguration process. The bitstream is processed by the configuration logic- a part of the FPGA that is not programmable in order to establish routing to and from instantiated elements by setting the state of memory cells, pass gates, and routing switches. The user logic is the FPGA's reconfigurable part and where the user-defined application operates. Reconfiguration of FPGAs is becoming increasingly popular particularly in networking applications and it is vital to provide security against malicious parties interfering with equipment functionality through this mechanism. Also, remote reconfiguration is attractive in such systems to offer new multimedia features or to repair eventual security vulnerabilities.