A 1.9nJ/bit, 5Mbps multi-standard ISM band wireless transmitter using fully digital PLL

This paper presents an energy efficient transmitter for multi-standard applications (IEEE802.15.4, BLE, 5Mbps) in ISM2.4GHz band. It incorporates a fully digital PLL with two point modulation to achieve upto 5Mbps data rate at 9.5mW power consumption (including all power management blocks) at 0dBm output power, leading to 1.9nJ/b efficiency. The proposed digital PLL uses a counter based area and power efficient re-circulating TDC, current reuse low area DCO using resistive tail, process compensated high speed divider, class-AB PA stages, and fully integrated on-chip LDOs. The entire transmitter occupies 0.35mm² Silicon area in a 65nm digital CMOS process.

I. Introduction

Ultra low power and energy efficient radio transceivers have found widespread use for wireless sensors, medical and other emerging applications [1]–[4]. This paper presents an energy efficient, multi-standard transmitter operating in ISM 2.4GHz band using fully digital PLL (DPLL) architecture. The transmitter meets the system requirements of IEEE802.15.4, Bluetooth low energy (BLE), enhanced data rate mode with data rates of 250kbps, lMbps, 5Mbps respectively. Two point modulation using DPLL provides two principal benefits for phase/frequency modulations: (a) Provision of completely matched digital injection capable of supporting data rates beyond the PLL's loop bandwidth without any complicated calibration loop, (b) Lower area, finer TDC resolution, design ease and scalability, that scale directly with technology node. However, these advantages of digital PLL are somewhat undermined by their high power consumption even at scaled CMOS nodes, along with the presence of spurious tones due to higher switching activities. These deficiencies of reported DPLLs in open literature have presented significant difficulty for their use in low power, low energy systems. In this paper, we present techniques to achieve a low power DPLL based digitally-intensive transmitter in 65nm standard CMOS technology that uses current-reuse DCO, dynamic logic based divider, counter based time to digital converter (TDC) and class-AB PA, consuming total power of 9. 5mW leading to a best in class energy efficiency of 1.9nJ/bit with DPLL consuming only 0.22mm² Silicon area.