2-D Compact Model for Drain Current of Fully Depleted Nanoscale GeOI MOSFETs for Improved Analog Circuit Design

Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance.

I. Introduction

Relentless miniaturization of MOS devices is the key to performance improvement that can be accomplished using innovative architectures and novel materials. Germanium-on-insulator (GeOI) MOSFETs cumulate both the advantages of bulk Ge channel [1]–[3] (augmented electron and hole mobilities) and on insulator substrate (better electrostatic control) [4]–[6]. Hence, these devices exhibit reduced short channel effects (SCEs) and can be scaled to advanced technology nodes. Furthermore, the threshold voltage of such devices can be tuned easily by adjusting the back-gate bias without controlling the doping level of the channel, thereby alleviating variability due to random dopant fluctuations [7]. To exploit the benefits of these transistors, we need an accurate and fast simulation of circuits built using such devices.