High-Performance SLS Nanowire TFTs With Dual-Gate Structure

Gate-all-around (GAA) sequential-lateral-solidification (SLS) nanowire (NW) thin-film transistor (TFT) devices with single-gate and dual-gate structures are fabricated and characterized. Compared with planar SLS TFT, owing to only one perpendicular grain boundary in each NW channel, GAA SLS NW TFT with single-gate structure can exhibit better performances when operated at low gate/drain voltage. However, it suffers from an obvious kink effect when operated at high gate/drain voltage because of the local electrical fields located at the sharp corners in GAA structure. Via dual-gate structure design, it clearly improves the performance of TFT device, which thus has a lower leakage current, a higher ON/OFF ratio, and an improved kink effect as compared with single-gate TFTs by avoiding the perpendicular grain boundaries and reducing electrical fields near channel/drain junction regions. In addition, the device reliability, such as the threshold voltage shift, subthreshold swing, and transconductance degradation under dc hot-carrier stress, is apparently improved by the proposed structure.

I. Introduction

Low-temperature poly-Si thin-film transistors (TFTs) are widely used as pixel-switching elements in active-matrix display panels. Recently, many high-performance TFTs are provided due to their potential use in 3-D circuit technology, liquid crystal display drivers, and system-on-panel applications [1], [2]. It is well known that the presence of grain boundaries in device channel always impacts the carrier mobility. Therefore, how to improve the mobility has become an important direction. Many techniques for controlling the grain size and grain-boundary location of polycrystalline silicon thin films are developed to improve the mobility and electrical performance. With controlled manipulation of the super-lateral-growth phenomenon, the sequential-lateral-solidification (SLS) process can effectively produce directionally solidified microstructure and location-controlled single-crystal-like region on Si film [3]–[6]. Previous literature exhibited that the large-grain poly-Si is crystallized by SLS process and a location-controlled irradiated zone with directionally solidified microstructure that can be formed on Si film [7], [8]. When the nitride spacers are used as nanoscale hard masks, single-crystal-like Si nanowire (NW) channel can be obtained by an anisotropic etching without any advanced lithography tool. In other words, the location-controlled irradiated zone is sufficiently large for complete inclusion of a short NW channel TFT device. Owing to the small amount of defects by thinning down the channel body and enhanced gate controllability over the channel, NW-based TFTs with multiple gates exhibited excellent performance [9]–[15]. When the NW channel is small enough , the NW channel body can be designed to be within one crystalline grain [7], [8]. However, for longer NW channel TFT device , there are many chances that the NWs meet with the grain boundary defects and intragrain defects in Si channel, and it will degrade the TFT characteristics. In addition, previous literature [16]–[18] indicated the field-enhanced carrier tunneling via novel gate structures led to faster program speeds for the and gate-all-around (GAA) nonvolatile memory as compared with the planar counterpart. Therefore, the local electrical field located at the sharp corners will degrade the performance of GAA TFT devices. Previous literature revealed that dual-gate structure can change electrostatic potential distribution and improve electrical characteristics [19]–[21]. In this paper, GAA SLS NW TFT devices with single-gate and dual-gate structures are fabricated. In addition to the reduction of electric field, for dual-gate structure, this design avoids the perpendicular grain boundary and a single-crystal-like NW channel is achieved. However, a NW channel with a perpendicular grain boundary is obtained in single-gate structure.