I. Introduction
With the great development of the VLSI technology, it enables integration of an increasing number of IP cores on a single die. Tens of cores are possible on a single chip multiprocessor (CMP), such as Intel's terascale processor [1] and Tilera's TILE64 processor [2]. Intel has built their Single-chip Cloud Computer CMP with 48 cores [3] and research chips with 80 cores [4]. Therefore, the number of the router is also increasing. But according to the prediction from an Intel commentator in [5], in the 100-billion transistor chips “20 billion of those transistors will fail in manufacture and a further 10 billion will fail in the first year of operation”. Thus, this high device failure rate means we must consider the fault-tolerant routing algorithm in the NoC.