I. Introduction
Under the nanometer process technology, accurate extraction of interconnect capacitance with 3-D field-solver algorithm becomes increasingly important for high-performance integrated circuit (IC) design. The field-solver algorithm for capacitance extraction can be classified into two categories: 1) the conventional deterministic algorithms based on boundary element method (BEM) [1]–[6], finite element method (FEM) [7], [8], etc., and 2) the floating random walk (FRW) algorithm with stochastic nature [9]–[20]. The deterministic algorithms are fast and accurate, but not suitable for large-scale structures due to the large demand of computational time and the bottleneck of memory usage.