Abstract:
Until now, various limited directory-based cache coherence protocols were proposed for medium- or large-scale multiprocessors while employing scalable directory memories....Show MoreMetadata
Abstract:
Until now, various limited directory-based cache coherence protocols were proposed for medium- or large-scale multiprocessors while employing scalable directory memories. For widely shared data, however, most protocols suffer from extraneous cache invalidates or updates due to insufficient pointers. We focus on large-scale mesh-connected multiprocessors built on top of wormhole and dimension ordered routing networks. In such networks, worms are major bricks for communications, which transit all the intermediate nodes on their way to a destination. From such an observation, we propose a new directory-based protocol DirQ with limited pointers, which can represent either one node or a set of nodes when being widely shared. For /spl radic/N/spl times//spl radic/N processors system, our protocol needs /spl Theta/(N/sup 3/2/ log N) bits for directory memory which is much more scalable compared to the full-map protocol. In terms of latency and traffic volume for cache coherence, our analytic models show that DirQ outperforms other limited protocols, and further comparable to the full-map one.
Published in: Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN'97)
Date of Conference: 20-20 December 1997
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-8186-8259-6
Print ISSN: 1087-4089
References is not available for this document.
Select All
1.
M. Tomašević and V. Miluntinovic, "Hardware Solutions for Cache Coherence" in Shared Memory Multiprocessor Systems, IEEE Computer Society Press, 1993.
2.
A. K Jones and P. Schwarz, "Experience using multiprocessor systems: a status report", ACM Computing Surveys, vol. 12, no. 2, pp. 121-165, 1980.
3.
J. Archibald and J.-L. Baer, "An Evaluation of Cache Coherence Solutions in Shared-bus Multiprocessors", ACM Trans. on Computer Systems, vol. 4, no. 4, pp. 273-298, 1986.
4.
D. Chaiken, C. Fields, K. Kurihara and A. Agarwal, "Directory-Based Cache Coherence in Large-Scale Multiprocessors", IEEE Computer, pp. 49-58, June 1990.
5.
D. Lenoski, J. Laudon, K. Gharachorloo, W. D. Weber, A. Gupta, J. Hennesy, et al., The Stanford Dash Multiprocessor. IEEE Computer, pp. 63-79, March 1992.
6.
A. Agarwal, "The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor", Proc. of Workshop on Scalable Shared Memory Multiprocessors, 1991.
7.
"Intel Supercomputer Systems Division" in Paragon XP/S Product Overview, Intel Corp., 1990.
8.
M Lucien, "Censier and Paul Feautrier. A New Solution to Cache Problems in Multicache Systems", IEEE Trans. on Computers, vol. C-27, no. 12, pp. 1112-1118, December 1978.
9.
A. Agarwal, R. Simoni, J. Hennessy and M. Horowitz, "An Evaluation of Directory Schemes for Cache Coherence", Proc. of the 15th Intl Symp. on Computer Architecture, 1988-June.
10.
A. Gupta, W.-D. Weber and T. Mowry, "Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes", Proc. of Intl Conf. on Parallel Processing, 1990.
11.
D. Chaiken, J. Kubiatowicz and A. Agarwal, "LimitLESS Directories: A Scalable Cache Coherence Scheme", Proc. of ASPLOS IV, 1991-April.
12.
D. V. James, A. T. Laundrie, S. Gjessing and G. S. Sohi, "Scalable Coherence Interface", IEEE Computer, vol. 23, no. 6, pp. 74-77, June 1990.
13.
D. Dai and D. K. Panda, "Reducing Cache Invalidation Overheads in Wormhole Routed dsms Using Multidestination Message Passing", Proc. of Intl Conf. on Parallel Processing, vol. 1, pp. 138-145, 1996-August.
14.
S. J. Eggers and R. H. Katz, "A Characterization of Sharing in Parallel Programs and Its Applications to Coherency Protocol Evaluation", Proc. of the 15th Intl Symp. on Computer Architecture, pp. 373-382, 1988-May.