A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS

This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline architecture, an on-chip digital background calibration is implemented to correct residue subtraction error in the seven MSB stages. An asynchronous clocking scheme realizes pipeline operation for higher throughput. The TDC was implemented in standard 0.13-μm CMOS technology and has a maximum throughput of 300 MS/s and a resolution of 1.76 ps with a total conversion range of 1.8 ns. The measured DNL and INL were 0.6 LSB and 1.9 LSB, respectively.

I. Introduction

Time-To-Digital CONVERTERs (TDCs) have been widely used as a fundamental circuit block in various applications such as equivalent-time sampling in oscilloscope [1], high energy physics [2], positron emission tomography (PET) imaging instruments [3]–[6], and all-digital phase-locked-loops (ADPLLs) [7]–[9]. Since TDC is an analog-to-digital converter (ADC) that receives input in the time domain, it is so difficult to achieve fine resolution, good linearity, wide conversion range, and high throughput simultaneously.