High-Performance Polycrystalline-Silicon Nanowire Thin-Film Transistors With Location-Controlled Grain Boundary via Excimer Laser Crystallization

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) are demonstrated using excimer laser crystallization to control the locations of grain boundaries two-dimensionally. Via the locally increased thickness of the amorphous-silicon (a-Si) film as the seeds, the cross-shaped grain boundary structures were produced among these thicker a-Si grids. The NW TFTs with one primary grain boundary perpendicular to the channel direction could be therefore fabricated to achieve an excellent field-effect mobility of 346 $\hbox{cm}^{2}/\hbox{V} \cdot \hbox{s}$ and an on/off current ratio of $\hbox{3} \times \hbox{10}^{9}$. Furthermore, the grain-boundary-location-controlled NW TFTs also exhibited better reliability due to the control of grain boundary locations. This technology is thus promising for applications of low-temperature poly-Si TFTs in system-on-panel and 3-D integrated circuits.

I. Introduction

Low-Temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) have attracted considerable attention for the applications in active-matrix flat-panel displays and 3-D integrated circuits (3-D ICs) [1]–[3]. Several technologies and device structures have been proposed to improve the device performance. The poly-Si nanowire (NW) TFTs have been fabricated to enhance gate controllability, and the short-channel effects and subthreshold leakage current can be suppressed owing to their high surface-to-volume ratio [4], [5]. Most of them used solid-phase crystallization (SPC) and thus induced the numerous grain boundaries as well as intragrain defects, resulting in poor performance [6]–[8]. Excimer laser crystallization (ELC) of amorphous silicon (a-Si) has been proven to be a promising method to produce high-quality silicon grains and led to better device performance. Therefore, the modified ELC technologies such as sequential lateral solidification (SLS) for controlling the location of grain boundary have been adopted on the fabrication of NW-based poly-Si TFTs [9], [10]. However, the NW TFTs fabricated with SLS exhibited large variations of device characteristics due to the randomly distributed grain boundaries along the channel direction since the SLS process controlled the location of the grain in only one dimension by lateral solidification. Fig. 1.

Schematic diagram of the key fabrication processes for the GBLC NW TFTs: a-Si island formation, a-Si deposition and ELC process, dummy oxide and nitride spacer formation, and NW channel and gate electrode formation.