Silicon-Based Dynamic Synapse With Depressing Response

A compact implementation of a dynamic charge transfer synapse cell, capable of implementing synaptic depression, is presented. The cell is combined with a simple current mirror summing node to produce biologically plausible postsynaptic potentials (PSPs). A single charge packet is effectively transferred from the synapse to the summing node, whenever a presynaptic pulse is applied to one of its terminals. The charge packet is “weighted” by a voltage applied to the second terminal of the synapse. A voltage applied to the third terminal determines the charge recovery time in the synapse, which can be adjusted over several orders of magnitude. This voltage determines the paired pulse ratio for the synapse. The fall time of the PSP is also adjustable and is set by the gate voltage of a metal-oxide-semiconductor field-effect transistor operating in subthreshold. Results extracted from chips fabricated in a 0.35-μm complementary metal-oxide-semiconductor process, alongside theoretical and simulation results, confirm the ability of the cell to produce PSPs that are characteristic of real synapses. The concept addresses a key requirement for scalable hardware neural networks.

I. Introduction

Biological research has accumulated an enormous amount of knowledge regarding the structure and the functions within the brain [1]. It is widely accepted that the basic processing units in the brain are neurons that are interconnected in a complex weblike structure. These neurons communicate by small voltage pulses where the timing of these pulses encodes information. Although the complexity of encoding and decoding within the brain still eludes neurobiologists, a range of computational operations is possible with spiking neural networks (SNNs), even with relatively primitive coding techniques [2]. This realization has stimulated significant research on the development and deployment of equivalent models that can be implemented in either hardware or software and used to inspire new paradigms for real-time computational networks. However, neural systems are difficult to model as they are composed of many nonlinear elements and have a substantial range of time constants. Therefore, their mathematical behavior cannot be solved analytically, and a more common approach is to employ the simulation of their functionality on a general-purpose computer [3]–[5]. Consequently, neural systems are predominately implemented in software running on personal computers and workstations. Nevertheless, implementing neural computing techniques in dedicated hardware has a number of important advantages [6]–[9]. For example, hardware implementation can provide a self-contained and physically robust solution for application areas where it would not be feasible or cost-effective to install a PC to run a neural processor. Biological implants, toys, autonomous robots for industry, exploration, and industrial process control are a few examples. More importantly, a hardware implementation approach to the realization of neural systems will facilitate the exploitation of the parallel processing capability associated with biological systems and consequently expand the application domain to real-time processing. Indeed, the implementation of large-scale NNs in hardware may provide for further insight into how certain functions in the brain work.