A dual-mode weight storage analog neural network platform for on-chip applications

On-chip trainable neural networks show great promise in enabling various desired features of modern integrated circuits (IC), such as Built-In Self-Test (BIST), security and trust monitoring, self-healing, etc. Cost-efficient implementation of these features imposes strict area and power constraints on the circuits dedicated to neural networks, which, however, should not compromise their ability to learn fast and retain functionality throughout their lifecycle. To this end, we have designed and fabricated a reconfigurable analog neural network (ANN) chip which serves as an expertise acquisition platform for various applications requiring on-chip ANN integration. With this platform, we intend to address the key cost-efficiency issues: a fully analog implementation with strict area and power budgets, a learning ability of the proposed architecture, fast dynamic programming of the weight memory during training, and high precision non-volatile storage of weight coefficients during operation or standby. We explore two learning structures: a multilayer perceptron (MLP) and an ontogenic neural network with their corresponding training algorithms. The core circuits are biased in weak inversion and make use of the translinear principle for multiplication and non-linear conversion operations. The chip is mounted on a custom PCB and connected to a computer for chip-in-the-loop training. We present measured results of the core circuits and the dual-mode weight memory. The learning ability is evaluated on a 3-input XOR classification task.

I. Introduction

Various realities of modern semiconductor manufacturing business necessitate the inclusion of dedicated on-chip circuitry for post-deployment monitoring — and potentially action-taking — of analog/RF ICs, in order to enhance their reliability, robustness, and trustworthiness. For example, circuit deployment in mission-critical applications (e.g. avionics, medicine) and sensitive environments (e.g. space) calls for a BIST method [1] such that the chip can assess its own functional health and issue alerts in case of malfunctions. Similarly, contemporary analog/RF ICs take an aggressive design approach in order to maximize performance, possibly at the expense of robustness, which is later compensated for through on-chip self-calibration and self-healing hardware [2] (i.e. tuning knobs). Finally, security concerns regarding the globalized IC supply chain, which may be vulnerable to malicious attacks (a.k.a. Hardware Trojans [3]), have sparked interest in adding hardware for monitoring operation trustworthiness. In the heart of these three problems, lies some form of low-cost on-chip intelligence, which acquires measurements through low-cost sensors and makes pass/fail decisions regarding correctness/trustworthiness, or selects appropriate tuning knob positions to ensure specification-compliant functionality. To this end, our research focuses on developing a low -cost analog neural network which can be integrated with the circuit in order to provide the aforementioned reliability, robustness and trustworthiness capabilities. Fig. 1. Top level chip architecture. The core includes synapses (S), neurons (N) and multiplexors for topology configuration. Peripheral circuits support network operation and programming.