The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET

In planar MOSFET, the optimization of finger length should be carried out with considering f_T, f_max and flicker noise because the noise degradation at STI edge effect appears below 1μm. In FinFET, the optimization of not only finger length but also the distance between gate and source, drain contact region and fin pitch are necessary to reduce parasitic resistance and capacitance. According to our measurement results, the flicker noise of FinFET decreases with scaling of fin width and it is possible to satisfy the 24nm technology node requirement in ITRS roadmap 2011 at fin width below 20nm.

Introduction

For analog and RF designer, higher and low flicker noise are attractive to realize the high performance circuit. The scaled planar MOSFET has lead to the higher operation frequency application. Recently, un-doped double gate MOSFETs, such as FinFET are promising candidates for scaling CMOS into the sub-32nm node and below because of its good cut-off characteristics and better scalability due to double gate mode operation. However, reported figure of merit of FinFET are lower than planar MOSFET [3], [4]. In this paper, we discuss device parameter to obtain high RF performance for planar MOSFET and FinFET. Additionally, structural merits of FinFET relative to flicker noise are discussed. (Keyword: Planar MOSFET, FinFET, RF, noise)