A self-test and self-repair approach for analog integrated circuits

With the continuous increase of integration densities and complexities, secure integrated circuits (ICs) are more and more required to guarantee reliability for safety-critical applications in the presence of soft and hard faults. Thus, testing has become a real challenge for enhancing the reliability of safety-critical systems. This paper presents a Self-Test and Self-Repair approach which can be used to tolerate the most likely defects of bridging type that create a resistive path between VDD supply voltage and the ground occurring in analog CMOS circuits during the manufacturing process. The proposed testing approach is designed using the 65 nm CMOS technology. We then used an operational amplifier (OPA) to validate the technique and correlate it with post layout simulation results.

I. Introduction

The constant advances in VLSI technology have given the capability to design and manufacture very complex integrated circuits that include digital, analog and mixed circuits in the same chip. The approach based on integrating all these components into a single chip is known as the system-on-a chip (SoC) approach design [1] [2]. Although this approach simplifies the design phase of the product, it increases the complexity of testing of the system, in particular testing of the analog blocks or analog functions embedded in mixed-signal or analog cores [2].