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Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects | IEEE Conference Publication | IEEE Xplore

Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects


Abstract:

For successful adoption of through-silicon-via-based 3D ICs, delay estimation techniques of 3D interconnects for early design stages are required. The 3D nets may connect...Show More

Abstract:

For successful adoption of through-silicon-via-based 3D ICs, delay estimation techniques of 3D interconnects for early design stages are required. The 3D nets may connect gates/macros placed far apart and through-silicon-vias (TSVs) have large parasitic capacitances. Thus, buffers are inserted to reduce interconnect delay. To make good decisions in early design stages, the estimation of buffered delay should be fast and reasonably accurate. However, there has been no buffered delay estimation work for 3D ICs that considers proper delay models and TSV RC parasitics. In this work, we investigate several analytical delay models for 3D net delay estimation. Then, based on analytical formula and our heuristic algorithm, we propose how to estimate the buffered delay for movable TSV cases and fixed TSV cases. The effectiveness of our delay estimation technique is demonstrated with various 3D nets. Compared with the van Ginneken buffer insertion based delay estimation, our estimation provides solutions about 750 times faster with almost the same estimated delay.
Date of Conference: 19-21 March 2012
Date Added to IEEE Xplore: 19 April 2012
ISBN Information:

ISSN Information:

Conference Location: Santa Clara, CA, USA

I. Introduction

As the physical limit for technology scaling approaches and the cost for IC fabrication soars, 3D IC is considered as a viable way to preserve Moore's law. The benefits of 3D ICs have been advocated and lots of researches have been done on material, fabrication, design methodology, testing and so on, for successful commercialization. For a fast adoption, designers may choose to partition existing designs into blocks then place them on different dies along with IP blocks. To enable this so-called block-level 3D IC design methodology, a reasonably good timing estimation technique is required in early design stages, such as architectural design space exploration, floorplanning, or timing-driven placement.

References

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