I. Introduction
As the physical limit for technology scaling approaches and the cost for IC fabrication soars, 3D IC is considered as a viable way to preserve Moore's law. The benefits of 3D ICs have been advocated and lots of researches have been done on material, fabrication, design methodology, testing and so on, for successful commercialization. For a fast adoption, designers may choose to partition existing designs into blocks then place them on different dies along with IP blocks. To enable this so-called block-level 3D IC design methodology, a reasonably good timing estimation technique is required in early design stages, such as architectural design space exploration, floorplanning, or timing-driven placement.