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Examination of novel high-voltage double-emitter horizontal current bipolar transistor (HCBT) | IEEE Conference Publication | IEEE Xplore

Examination of novel high-voltage double-emitter horizontal current bipolar transistor (HCBT)


Abstract:

Electrical characteristics of a novel high-voltage double-emitter HCBT structure integrated with the standard 180 nm bulk CMOS are presented. 3D collector charge sharing ...Show More

Abstract:

Electrical characteristics of a novel high-voltage double-emitter HCBT structure integrated with the standard 180 nm bulk CMOS are presented. 3D collector charge sharing is used to achieve intrinsic base shielding and to limit the electric field across the intrinsic base-collector junction. This is accomplished by the transistor layout i.e. the mask design. Transistors with BVCEO =12.6 V, VA=301 V and fT=12.7 GHz are fabricated in a standard HCBT BiCMOS process flow without the use of the additional lithography masks. Physical behavior of the transistor is thoroughly examined by 3D device simulations.
Date of Conference: 09-11 October 2011
Date Added to IEEE Xplore: 17 November 2011
ISBN Information:

ISSN Information:

Conference Location: Atlanta, GA, USA

I. Introduction

Integration of high breakdown voltage and high speed bipolar transistors with standard CMOS is highly desirable as it results in the broader application spectrum of the BiCMOS technology. In standard vertical-current bipolar transistor structures based on the super-self-aligned transistor (SST), different breakdown voltage devices are typically obtained by the different parameters of Selectively Implanted Collector (SIC) [1], which usually requires additional lithography masks. On the other hand, power transistors such as GAT [2] and TBSBT [3] take the advantage of the intrinsic base shielding effect to obtain very high collector-emitter breakdown voltage In these structures, the extrinsic base surrounds lightly doped collector and is made in the form of deep trenches. Lateral electric field from the extrinsic base fully depletes the collector region and electrostatically shields the intrinsic base from the collector voltage. In this way, is improved and base width modulation suppressed, allowing fabrication of a thinner intrinsic base resulting in the transistor with high current gain (ß) cutoff frequency and simultaneously. Similar effect of limited electric field at the intrinsic base-collector junction is observed in vertical-current SiGe BJTs made on thin SOl [4], where collector charge is limited by the SOI thickness and potential is pinned at the Si-Si02 interface when collector is fully depleted.

References

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