I. Introduction
Integration of high breakdown voltage and high speed bipolar transistors with standard CMOS is highly desirable as it results in the broader application spectrum of the BiCMOS technology. In standard vertical-current bipolar transistor structures based on the super-self-aligned transistor (SST), different breakdown voltage devices are typically obtained by the different parameters of Selectively Implanted Collector (SIC) [1], which usually requires additional lithography masks. On the other hand, power transistors such as GAT [2] and TBSBT [3] take the advantage of the intrinsic base shielding effect to obtain very high collector-emitter breakdown voltage In these structures, the extrinsic base surrounds lightly doped collector and is made in the form of deep trenches. Lateral electric field from the extrinsic base fully depletes the collector region and electrostatically shields the intrinsic base from the collector voltage. In this way, is improved and base width modulation suppressed, allowing fabrication of a thinner intrinsic base resulting in the transistor with high current gain (ß) cutoff frequency and simultaneously. Similar effect of limited electric field at the intrinsic base-collector junction is observed in vertical-current SiGe BJTs made on thin SOl [4], where collector charge is limited by the SOI thickness and potential is pinned at the Si-Si02 interface when collector is fully depleted.