Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire

For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low leakage, tunability in drain current, as well as “AND” gate functionality with 50% reduction in area for both n- and p-type MOSFETs. The twin-gate device structure is also promising for implementing other device types such as stacked SONOS memory and tunneling FET. We anticipate that our vertically integrated device architecture will provide unique opportunities for realizing ultra-dense CMOS logic on a single nanowire.

I. Introduction

Gate-All-Around (GAA) nanowire transistors are one of the most promising nonplanar nanoscale device structures that have demonstrated excellent performance, scalability, and immunity to short-channel effects [1]. The near-ideal subthreshold slope (SS) and high ON/OFF ratio make them ideal candidates for various CMOS applications. From a high-density integration point of view, vertical nanowire transistors have the smallest possible device area (, where is the half-pitch) [2]. Moreover, the vertical GAA architecture has the greatest potential for stacking devices on top of each other and therefore opens up the possibility of realizing true 3-D integration [3] and novel logic circuit design [4]–[7].