Contact-Resistance Reduction for Strained n-FinFETs With Silicon–Carbon Source/Drain and Platinum-Based Silicide Contacts Featuring Tellurium Implantation and Segregation

Tellurium (Te) implantation was introduced to tune the effective electron Schottky barrier height (SBH) Φ_Bⁿ of platinum-based silicide (PtSi) contacts formed on n-type silicon-carbon (Si:C). Te introduced by ion implantation prior to Pt deposition segregated at the PtSi:C/Si:C interface during PtSi:C formation. The presence of Te at the PtSi:C/Si:C interface leads to a low Φ_Bⁿ of 120 meV for PtSi:C contacts. The integration of Te-segregated PtSi:C contacts on strained n-channel fin field-effect transistors (FinFETs) with Si:C source/drain (S/D) stressors achieves the lowering of the parasitic series resistance R_SD by ~62% and increases the saturation drive current by ~22%. The Te-segregated contact-resistance reduction technology does not degrade the short-channel effects and positive-bias temperature instability characteristics of n-FinFETs with Si:C S/D. As PtSi has a low SBH for holes and is a suitable contact for p-FinFETs, this new contact-resistance reduction technology has potential to be introduced as a single-metal-silicide dual-barrier-height solution for future complementary metal-oxide-semiconductor FinFET technology.

I. Introduction

High Parasitic source/drain (S/D) series resistance is one of the challenges for the continual performance improvement of FET technology [1]. Multiple-gate FETs such as FinFETs would be adopted for the control of short-channel effects (SCEs) in high-volume manufacturing at the 22-nm technology generation and beyond [2]–[7]. With the use of the narrow fin width , the issue of high may be further aggravated [8]–[10]. The increase in with decreasing may be a bottleneck for achieving high drive-current performance in aggressively scaled FinFETs. The contact resistance at the silicide/heavily doped S/D interface is a major contributor to [11]. Thus, it is imperative to explore solutions to minimize . As is an exponential function of the Schottky barrier height (SBH) at the silicide/heavily doped S/D interface, silicide materials that provide low SBH on and Si are needed to achieve low in p-channel and n-channel FETs (p-FET and n-FET), respectively, in CMOS technology.