High-Speed Multilevel nand Flash Memory With Tight $V_{\rm th}$ Distribution Using an Engineered Potential Well and Forward-Bias Adjusted Programming

This paper reports a high-speed multilevel-cell nand Flash memory device using a Si- SiO₂-TiN- TiO₂-SiO₂-TaN (SOTTOT) engineered potential well (EW). The SOTTOT EW Flash memory device has very fast cell programming speed and good data retention. A 16-kbit nand memory block using SOTTOT cells was programmed using a forward-bias-adjusted programming scheme, which enables bit adjustability during page programming to suppress the development of fast bits. The SOTTOT memory block shows fast programming speed (~40 μs/page), tight threshold voltage (V_th) distribution (~0.22 V/level), and clear V_th-level margins (~0.9 V) for the eight-level programming. The SOTTOT memory block also shows good resistance against pass/read disturbances as well as good ten-year data retention at an ambient temperature of 75 °C throughout 10⁵ programming/erasing cycling.

I. Introduction

Multilevel-Cell (MLC) nand Flash memory devices unify promising scalability and condensed data density, providing a favorable approach for mass data storage [1]–[7]. MLC storage programs a selected cell in a memory array to any -value (with ) different threshold voltages so that each cell stores bits of digital information. As a result, the data density is condensed, despite the device dimension, and the cost per bit is reduced for any lithographic technology generation [3]. In order to accomplish MLC storage for nand memory arrays, various write-and-verify (WAV) schemes have been developed to pursue the precise programming of multiple levels [4]–[6]. Wear leveling has been developed to improve the programming/erasing (P/E) endurance [7], and error-correcting techniques have been developed to improve the long-term data retention [7]–[9]. On the other hand, MLC nand Flash memory devices using floating-gate and polysilicon–oxide–nitride–oxide–silicon (SONOS) memory cells are underdeveloped in terms of the programming speed due to WAV cycling. For example, it takes 200–300 to program a single-level cell, whereas it can take 600–900 to program an MLC [7]. Moreover, MLC nand Flash memory devices may suffer from page programming disturbances [5], [6]. For example, a random page of memory cells are programmed simultaneously using the identical word-line (WL) bias condition, as shown in Fig. 1(a). Nevertheless, the programmed threshold voltages read from all the bit lines (BL) must present a certain spread due to various (processing, environmental, etc.) disturbances, as shown in Fig. 1(b). The underprogrammed and overprogrammed cells are known usually as tail bits and fast bits, respectively. If WAV schemes complete the programming after all tail bits are programmed, as shown in Fig. 1(b), the fast bits may spread so far that they disturb the precise control of multiple levels. This can be regarded as a type of programming disturbance. Such programming disturbances may be tolerable for single-level-cell nand Flash memory devices, but it is critical for MLC nand Flash memory devices, particularly for high density, e.g., 8- and 16-level MLC storage. In this regard, memory cells with faster programming speed are desired to speed up the WAV cycle, and programming schemes that suppress the programming disturbance are needed to improve the MLC control. Fig. 1.

(a) Equivalent circuit diagram of the experimental memory block. (b) Illustration of the tail bits, fast bits, and programming disturbances for nand Flash memory devices.