Low power pipelined FFT architecture for synthetic aperture radar signal processing

A new FFT architecture for SAR (Synthetic Aperture Radar) signal processing is presented. The proposed architecture adopts several new techniques for low power operation and high throughput. A storage element and Delay Locked Loop (DLL) are newly designed for a constant geometry radix-4 pipelined DIF FFT architecture. The storage element uses a ping-pong scheme with two 16 KB SRAMs, each having an interleaved architecture. The data-path is designed to get the highest throughput with the smallest power consumption. By simulations, it is verified that the proposed FFT architecture enables 4096 point FFT operation in 336.04 msec by cascading six chips in series.