Abstract:
MOS capacitance measurements are very fundamental characterization methods for MOS and FET structures. This paper discusses the effects of a finite bias sweep rate on qua...Show MoreMetadata
Abstract:
MOS capacitance measurements are very fundamental characterization methods for MOS and FET structures. This paper discusses the effects of a finite bias sweep rate on quasi-static and high-frequency (HF) capacitance-voltage (C-V) measurements. As typically measured, a finite sweep rate causes the transition region from inversion to depletion of the quasistatic C-V curve to be shifted by several tenths of a volt along the bias voltage axis. The physical origin of this shift as well as a model to account for the effect is discussed. In order to understand quasi-static MOS C-V measurements and to extract fundamental parameters such as substrate doping density and polysilicon depletion effects from C-V measurements, these bias sweep rate effects must be understood and taken into account.
Published in: IEEE Transactions on Electron Devices ( Volume: 44, Issue: 6, June 1997)
DOI: 10.1109/16.585558
Citations are not available for this document.
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Cites in Papers - IEEE (3)
Select All
1.
Xiongfei Meng, Resve Saleh, Karim Arabi, "Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.11, pp.1581-1588, 2008.
2.
Karim Arabi, Resve Saleh, Xiongfei Meng, "Power Supply Noise in SoCs: Metrics, Management, and Measurement", IEEE Design & Test of Computers, vol.24, no.3, pp.236-244, 2007.
3.
T. Matsuda, R. Takezawa, K. Arakawa, M. Yasuda, T. Ohzone, E. Kameda, "Comparison of interface trap density measured by capacitance/subthreshold/charge-pumping methods for n-MOSFETs with Si-implanted gate-SiO/sub 2/", ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153), pp.65-70, 2001.
Cites in Papers - Other Publishers (11)
1.
Aditya K. Bhat, Hyun-Seop Kim, Abhishek Mishra, Matthew D. Smith, Michael J. Uren, Martin Kuball, "Analysis of interface trap induced ledge in β-Ga2O3 based MOS structures using UV-assisted capacitance–voltage measurements", Journal of Applied Physics, vol.135, no.19, 2024.
2.
Sorin Cristoloveanu, "The pseudo-MOSFET", Fully Depleted Silicon-On-insulator, pp.141, 2021.
3.
L. Pirro, I. Ionica, G. Ghibaudo, X. Mescot, L. Faraone, S. Cristoloveanu, "Interface trap density evaluation on bare silicon-on-insulator wafers using the quasi-static capacitance technique", Journal of Applied Physics, vol.119, no.17, pp.175702, 2016.
4.
"The MOS Structure", Silicon Devices and Process Integration, pp.213, 2009.
5.
Yi-Mu Lee, Yider Wu, "Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films", Applied Surface Science, vol.254, no.15, pp.4591, 2008.
6.
Jinwoo Kim, Seokhoon Kim, Hyunseok Kang, Jihoon Choi, Hyeongtag Jeon, Mannho Cho, Kwunbum Chung, Sungkwun Back, Kyungdong Yoo, Choelhwyi Bae, "Composition, structure, and electrical characteristics of HfO[sub 2] gate dielectrics grown using the remote- and direct-plasma atomic layer deposition methods", Journal of Applied Physics, vol.98, no.9, pp.094504, 2005.
7.
Yi-Mu Lee, Yider Wu, Gerald Lucovsky, "Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress", Microelectronics Reliability, vol.44, no.2, pp.207, 2004.
8.
Yi-Mu Lee, Yider Wu, Choelhwyi Bae, Joon Goo Hong, Gerald Lucovsky, "Structural dependence of breakdown characteristics and electrical degradation in ultrathin RPECVD oxide/nitride gate dielectrics under constant voltage stress", Solid-State Electronics, vol.47, no.1, pp.71, 2003.
9.
S. Dailey, A.P. Monkman, I.D.W. Samuel, "Electrical Characterisation of polymer heterojunction light-emitting diodes", Synthetic Metals, vol.102, no.1-3, pp.945, 1999.
10.
Yider Wu, Gerald Lucovsky, "Aggressively Scaled P-Channel Mosfets With Stacked Nitride-Oxide-Nitride, N/O/N, Gate Dielectrics", MRS Proceedings, vol.567, 1999.
11.
M. Schulz, "Electrical characterization of the SiO2Si system", Microelectronic Engineering, vol.40, no.3-4, pp.113, 1998.
