I. Introduction
Multilevel inverter topologies are experiencing increased application in the industrial environment, particularly in high-power drive systems [1]–[4]. The main advantages of these inverters are improving quality of voltage waveforms and an increase in the dc-link voltage for a given blocking voltage capacity of the semiconductors. Generation of voltage vectors in multilevel inverters requires taking into consideration all of the phenomena which have an influence on the accuracy of the output vectors. While the neutral point clamped (NPC) multilevel inverter (Fig. 1) converts higher voltages using devices with lower rating, the dc-link voltage balancing problem seriously limits the applicability of these inverters if not solved. The dc-link voltage unbalance causes an increase of the voltage stress on switching devices and additional harmonic distortion in the inverter output voltage. To maximize the performance of the three-level inverter, the voltages of the series connected dc-link capacitors should be equal.
Three-phase NPC inverter.