A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC

This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real-time program trace compressor, named trace-capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource and power consumption. The TC-cache can be configured to work simultaneously as the instruction cache and the trace compressor, named the online mode, or exclusively as the trace compressor, named the bypass mode. The RTL implementation of a 4 KB trace-capable instruction cache, a 4 KB data cache, and an academic ARM processor core has been accomplished. The experiments show that the TC-cache achieves average compression ratio of 90 percent with a very small hardware overhead of 3,652 gates (1.1 percent). It takes only 0.2 percent additional system power for the online mode operation. In addition, the trace support circuit does not impair the global critical path. Therefore, the proposed approach is a highly feasible on-chip debugging/monitoring solution for SoCs, even for cost-sensitive ones such as consumer electronics. Furthermore, the same concept can be applied to the data cache to compress the data address trace as well.

1 Introduction

To debug or analyze a software program running in a processor-based system-on-chip (SoC), it is often necessary to collect the program execution trace directly inside the SoC in real time. However, the problem is that the volume of the real-time trace grows so rapidly that it is impractical to store the trace on chip or send it outside through limited I/O pins. Therefore, various techniques have been proposed to reduce the trace volume directly in hardware. A straightforward approach is to employ a dedicated hardware compressor, which implements some compression algorithms such as the Lempel-Ziv (LZ) algorithm [1]. However, the hardware cost is very high.