Performance analysis of a low implementation complexity digital filter structure

It is well known that lattice filters have excellent finite word length properties and that there are five elementary lattice building blocks. A lattice structure may yield very different figures of performance when different elementary lattice blocks are used. This allows us to optimize the structure w.r.t. these elementary blocks. In this paper, a new lattice configuration is proposed, in which the traditional tapped/injected numerator structure with each stage realized using an optimally chosen one-multiplier elementary lattice block in the sense that the signal power ratio of the structure is minimized. For an Nth order filter, such a structure possesses only 2N +1 multipliers. Simulation results show that the optimized structure outperforms the classical tapped and injected numerator lattice structures, in which two-multiplier elementary lattice blocks are utilized, in terms of reducing implementation complexity and minimizing the signal power ratio.

I. Introduction

Finite word length (FWL) effects have been a critical issue in digital filter implementation for many decades. A well-designed digital filter can be implemented with different structures¹

Throughout this paper, a filter structure means a way with which the filter output is computed for a given input signal.

. Although those structures are totally equivalent when implemented in infinite precision, different realization structures may yield very different performance to the filter that practically has to be implemented with a finite precision device such as a fully customed ASIC. It is well known that a digital filter can be synthesized directly from its input-output difference equation. This method is so simple that the filter coefficient values can be obtained directly by inspection from the filter z-transform transfer function, but suffers greatly from the FWL effects such as roundoff noise, parameter sensitivity and overflow problems [1], [2]. It has been noted that the optimal roundoff noise state-space realizations [3], [4] can reduce the FWL effects significantly but they are not efficient for implementation since they have too many parameters to implemented. In fact, those realizations generally require multiplications and additions to implement an Nth order IIR digital filter. To solve this problem, a lot of effort has been made to achieve sparse optimal structures [5], [6]. Form a practical point of view, it is desired to design a filter with such a structure that is not only simple, but also yields a high performance against the FWL effects [7] - [9].