Design of charge pump circuit in low-voltage CMOS process with suppressed return-back leakage current

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide overstress problem in low-voltage CMOS process. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide reliability problem, the new proposed charge pump circuit is suitable for the applications in low-voltage CMOS IC products.

I. Introduction

Charge pump circuits can generate the voltage higher than the normal power supply voltage (VDD) or lower than the ground voltage (GND) in a chip, which were usually used to write or erase data in the nonvolatile memory. Moreover, charge pump circuits are also used in power management blocks and the driver ICs for liquid-crystal-display (LCD) panels [1].