A Fully Fledged TDC Implemented in Field-Programmable Gate Arrays

The motivation of this paper is to implement a fully fledged time-to-digital converter (TDC) in a field-programmable gate array from Xilinx Virtex 4 family with self-test and temperature variation compensation features. The TDC resolution is temperature and supply voltage dependent which, to a large part, is compensated. A self-test procedure, which covers a temperature range of 30 °C to 60 °C is used to determine the compensation constants. After compensation and integral nonlinearity (INL) calibration, the TDC presents a timing resolution of 25 ps RMS or 50 ps per LSB. A total of 9 channels TDCs are implemented in a single FPGA.

I. Introduction

Based on the principle of time interpolation, various time-to-digital-converter designs have been implemented in field-programmable gate arrays (FPGAs) [1]–[10], using the basic or auxiliary resources of the FPGA. It is a good choice to implement TDC in an FPGA due to its low cost, fast development cycle, and flexibility of reconfiguration. Previous research on TDCs in an FPGA has been carried out in our laboratory, using the dedicated carry-lines to perform time interpolation and obtaining a timing resolution of 50 ps root mean square (RMS) [9].