I. Introduction
Along WITH THE downscaling of the minimum feature size of modern CMOS technologies, the supply voltage is scaled down accordingly to reduce power dissipation. Reducing the supply voltage, however, increases the design effort and the power consumption for analog circuits even when the required performance is kept constant [1]. Therefore, increasing effort is spent to shift the analog complexity toward the digital domain in an attempt to reduce power consumption while increasing speed and accuracy. Specifically for analog-to-digital conversion (ADC), this strategy has led to the use of oversampled analog-to-digital converters where amplitude quantization is traded for increased time resolution. Converting the amplitude information of the original signal to the time domain replaces a high-precision analog amplitude quantizer with a high-speed 1-bit comparator, significantly reducing the analog complexity.