A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion | IEEE Journals & Magazine | IEEE Xplore

A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion


Abstract:

An analog-to-digital conversion (ADC) scheme based on asynchronous ΔΣ modulation and time-to-digital conversion is presented. An asynchronous ΔΣ modulator translates the ...Show More

Abstract:

An analog-to-digital conversion (ADC) scheme based on asynchronous ΔΣ modulation and time-to-digital conversion is presented. An asynchronous ΔΣ modulator translates the analog input to an asynchronous duty-cycle modulated signal. Next, the edge locations are digitally measured using a time-to-digital converter (TDC). This information is then digitally processed into a conventional digital signal. The performance of this novel ADC scheme is theoretically analyzed and verified with simulations. With the proposed digital demodulation algorithm, 11-bit resolution can be obtained with an overcycling ratio (OCR) of only four, which is suitable for high bandwidth applications such as very high bit-rate digital subscriber line (VDSL). When a higher OCR can be tolerated, a gated ring-oscillator (GRO) TDC with an inherent first-order noise shaping property is suggested in combination with a digital continuous-time moving-average (CTMA) filter. This allows for resolutions in excess of 13 bits, which is suitable for ADSL2+. The proposed technique shifts the complexity toward the digital domain, leading to more compact ADC and reduced power consumption, and is, therefore, particularly suited for ADC in ultralow-voltage nanometer technologies that are used for high-speed data communication applications.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 57, Issue: 9, September 2010)
Page(s): 2404 - 2412
Date of Publication: 08 March 2010

ISSN Information:


I. Introduction

Along WITH THE downscaling of the minimum feature size of modern CMOS technologies, the supply voltage is scaled down accordingly to reduce power dissipation. Reducing the supply voltage, however, increases the design effort and the power consumption for analog circuits even when the required performance is kept constant [1]. Therefore, increasing effort is spent to shift the analog complexity toward the digital domain in an attempt to reduce power consumption while increasing speed and accuracy. Specifically for analog-to-digital conversion (ADC), this strategy has led to the use of oversampled analog-to-digital converters where amplitude quantization is traded for increased time resolution. Converting the amplitude information of the original signal to the time domain replaces a high-precision analog amplitude quantizer with a high-speed 1-bit comparator, significantly reducing the analog complexity.

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