Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of bulk CMOS devices with and without e-SiGe/CESL stressors has been minimized. The presence of TSV caused no significant changes in Cu/ELK reliability. These excellent characteristics suggest the 300mm 3D-IC processes are promising and suitable for adoption in next generation integrated circuits and interconnects.

Introduction

While IC foundries gear up for 28 nm node to keep pace with Moore's law, the TSV technology is proposed as one solution to maintain the momentum of growth in logic density for state-of-the-art chips [1]. As the result of the shorter interconnect length, interconnect delay and power consumption are expected to decrease as well. In addition, TSV-based three-dimensional integrated circuit (3D-IC) is envisioned as a paradigm of “More than Moore” and heterogeneous integration.