FPGA implementation of Rijndael algorithm using reduced residue of prime numbers

This paper describes the field programmable gate array (FPGA) implementation of Rijndael algorithm based on a novel design of S-box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-box with reduced residue of prime number adds more confusion to the entire process of Rijndael and makes it more complex and immune to algebraic attacks. The target hardware used in this paper is state-of-the-art Xilinx Virtex-5 XC5VLX50 FPGA. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices.

I. Introduction

SINCE its inception, encryption has evolved within many fields especially in the field of communications and security networks. For security and fast transmission of data over an insecure path, cryptography methods have been used so far. For this reason, many researchers [1]–[3] are trying to implement secure, fast and efficient cryptographic algorithms in hardware using very high speed integrated circuit hardware description language (VHDL) or Verilog. Rijndael is the new Advanced Encryption Standard (AES) algorithm which was developed by Vincent Rijmen and Joan Daeman [4]. Rijndael consists of 128 block length of bits and supports 128, 192 and 256 key length bits. The 128 bits are organized into state matrix which is of the size of . This algorithm starts with initial transformation of state matrix followed by nine iteration of rounds. A round consists of four transformations: Byte Substitution (SubBytes), Row Shifting (ShiftRows), Mixing of columns (MixColumns) and followed by addition of Round Key called (AddRoundKey). From each round, a round key is generated from the original key through key scheduling process. The last round consists of SubBytes, ShiftRows and AddRoundKey transformation. SubBytes transformation is implemented using S-Box, which is computationally intensive and consumes more than 75% of the Field Programmable Gate Array (FPGA) resources [1].