Abstract:
The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determini...Show MoreMetadata
Abstract:
The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 /spl mu/m/spl times/6 /spl mu/m to 20 /spl mu/m/spl times/20 /spl mu/m fabricated in a standard 2 /spl mu/m double-poly CMOS process available through MOSIS. For a size of 6 /spl mu/m/spl times/6 /spl mu/m, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%. For the 20 /spl mu/m/spl times/20 /spl mu/m size, we observed that those capacitors that fell within 1 standard deviation of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching.
Published in: 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96
Date of Conference: 15-15 May 1996
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-3073-0
References is not available for this document.
Select All
1.
P. E. Allen and E. Sánchez-Sinencio, Switched Capacitor Circuits, New York:Van Nostrand Reinhold, 1984.
2.
J. L. McCreary and P. R. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques: Part I", IEEE Journal of Solid-State Circuits, vol. 10, pp. 371-379, Dec. 1975.
3.
R. E. Suarez, P. R. Gray and D. A. Hodges, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques: Part II", IEEE Journal of Solid-State Circuits, vol. 10, pp. 379-385, Dec. 1975.
4.
R. McCharles and D. A. Hodges, "Charge Transfer Circuits for Analog LSI", IEEE Transactions on Circuits and Systems, vol. 25, pp. 490-497, July 1978.
5.
M. J. McNutt, S. LeMarquis and J. L. Dunkley, "Systematic Capacitance Matching Errors and Corrective Layout Procedures", IEEE Journal of Solid-State Circuits, vol. 29, pp. 611-616, May 1994.
6.
C. Mead, Analog VLSI and Neural Systems, MA, Reading:Addison-Wesley, 1989.
7.
T. Shibata and T. Ohmi, "A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", IEEE Transactions on Electron Devices, vol. 39, pp. 1444-1455, June 1992.
8.
K. Yang and A. G. Andreou, "Subthreshold Analysis of Floating-Gate MOSFET's", Proceedings of the Tenth Biennial University Government Industry Microelectronics Symposium, pp. 141-144, 1993-May.
9.
E. A. Vittoz, "The Design of High-Performance Analog Circuits on Digital CMOS Chips", IEEE Journal of Solid-State Circuits, vol. SC-20, pp. 657-665, June 1985.
