Transistor-level test calculation for CMOS circuits

The paper presents a test calculation principle which serves for producing tests of transistor-level faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting control lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck short (short circuit) behavior. In this paper only combinational logic circuits are taken into consideration. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program.

I. INTRODUCTION

Due to the ever increasing complexity of digital integrated circuits, associated with the rapid development in their manufacturing processes, the importance of testing for correct functioning is steadily increasing. All this implies new fault models which require new methods in test design. The fulfillment of this requirement is especially important in the field of VLSI CMOS circuits which are widely used in the modern hardware construction.