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Soft error robust impulse and TSPC flip-flops in 90nm CMOS | IEEE Conference Publication | IEEE Xplore

Soft error robust impulse and TSPC flip-flops in 90nm CMOS


Abstract:

We propose an impulse flip-flop and a true single-phase clock (TSPC) flip-flop that are soft error robust. Each flip-flop consists of a unique transfer unit and a soft er...Show More

Abstract:

We propose an impulse flip-flop and a true single-phase clock (TSPC) flip-flop that are soft error robust. Each flip-flop consists of a unique transfer unit and a soft error robust 8-transistor Quatro latch. The transfer unit of the impulse flip-flop uses the clock signal and its complement to generate a narrow voltage pulse that enables writing the data into the Quatro latch. In contrast, the transfer unit of the TSPC flip-flop uses only the clock signal to conditionally pass the data into the Quatro latch. The flip-flops exhibit as much as 56% lower power-delay product when compared with a recently reported soft error robust flip-flop. The maximum area overhead of the proposed flip-flops is only 10% with respect to a master-slave D flip-flop. Post-layout simulations in 90nm CMOS technology confirms the functionality of the proposed flip-flops while an accelerated radiation test on an SRAM chip shows 47x lower soft error rate in the Quatro latch used in the proposed flip-flops.
Date of Conference: 13-14 October 2009
Date Added to IEEE Xplore: 20 November 2009
ISBN Information:
Conference Location: Ottawa, ON, Canada

I. Introduction

Low signal charge, which results from the reduced supply voltage and small node capacitance, makes nanoscale integrated circuits extremely susceptible to single event transients (SETs) [1], [2]. SETs are primarily caused by alpha particles and cosmic neutrons, which originate from package materials and intergalactic rays, respectively. As these particles pass through the silicon substrate, they generate extra electron-hole pairs (EHP) through direct or indirect ionization [3]. The EHPs get collected by sensitive nodes (e.g., reverse biased pn-junctions) of a circuit and create a voltage transient at the node. Fig. 1 shows such an event at the slave latch in a typical master-slave D flip-flop. When the amplitude and duration of the transient is large, it alters the stored value in the latch, causing a single event upset (SEU). A SEU is also referred to as a ‘soft error’ as it does not permanently damage the device. However, soft error can lead to system malfunctions and as such, state-of-the-art microprocessors require soft error protection [4].

References

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