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A Reconfigurable Platform for MPEG-4 Encoder Based on SOPC | IEEE Conference Publication | IEEE Xplore

A Reconfigurable Platform for MPEG-4 Encoder Based on SOPC


Abstract:

The appearance of the new MPEG-4 standard offers opportunities for real-time implementations of MPEG-4 encoders suitable for a wide range of applications, including video...Show More

Abstract:

The appearance of the new MPEG-4 standard offers opportunities for real-time implementations of MPEG-4 encoders suitable for a wide range of applications, including video conferencing, digital storage media, television broadcasting, Internet streaming, and communication. With the rapid development of FPGA, SOPC has been paid great attentions in the area of image and video processing in recent years. A parallel MPEG-4 Simple Profile encoder for FPGA based System-onChip (SOC) is presented. The architecture is truly scalable and is based on a vendor-independent intellectual property (IP) block interconnection network. Also, several key modules of MPEG-4 are integrated into an efficient platform in hardware/software codesign fashion. The hardware platform utilized to design the system is an SOPC board, which includes an FPGA chip of model EP2C35F484C8, an Ethernet controller and a camera interface. Finally, the encoder has been tested on the Altera NIOS II development board and can work up to 100 MHz. Implementation results show that this platform provides enough resources and speed to implement even complex multimedia embedded systems in real time.
Date of Conference: 17-19 October 2009
Date Added to IEEE Xplore: 30 October 2009
ISBN Information:
Conference Location: Tianjin, China
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I Introduction

Video is becoming an essential part of a wide spectrum of the multimedia embedded systems. Digital video has been paid great attentions in the area of image and video processing as opposed to analog video, because it is easier to transmit access, store and manipulate visual information in a digital format. There is, however, a key obstacle to using digital video which is the enormous amount of data required to represent video in digital format. Compression of the digital video, therefore, is an inevitable solution to overcome this obstacle. Consequently, video compression algorithms, including ITU-T H.261, H.263, ISO/IEC MPEG-1, MPEG-2 and MPEG-4, have been developed. They has emerged with a view to reduce the data rate to a manageable level by taking advantage of the redundancies present both spatial and temporal domains of the digital video [1].

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