Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET

In this paper, detailed analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET are described. The FinFET with narrow fin width such as below 30 nm is attractive for scaled CMOS because of double gate structure. Additionally, the flicker noise of FinFET decreases and the temperature dependence of the noise become smaller as the fin width becomes narrower. According to our measurements and simulation analysis, these are because the vertical electrical field from channel to gate electrode has relaxed with narrowing of fin width. The FinFET with narrow fin width is attractive for not only digital but also RF/analog circuits design because of good cut-off characteristics and lower flicker noise.

I. Introduction

FinFET is one of the candidates for CMOS device structure in 22 nm technology node and beyond, because of its good cut-off characteristics and better scalability by double gate mode operation [1]–[3]. FinFET on bulk Si substrate (bulk-FinFET) has many advantages compared to the FinFET on SOI substrate, such as lower wafer cost and the ease of the combination with conventional planar bulk CMOS devices. On the other hand, RF and mixed signal (MS) application of CMOS has been widely used because the cut-off frequency (fr) is increased by the scaling down of MOSFET. The study of RF and analog characteristics for FinFET are important for the design of digital and RF/analog circuits integrated in the same chip [4], [5]. In conventional planar bulk CMOS devices, the geometry parameters related to flicker noise are gate length, gate width and gate capacitor. FinFET however has an additional parameter such as fin width. In this paper, fin width dependence of the noise is reported and the mechanism are analysed by combination of measurements and simulation results of the substrate bias and temperature dependence.