I. Introduction
Generally, most receivers need a reference clock, which may be supplied by a transmitted signal or fed by external clock sources such as crystals. However, the former needs an additional channel to transmit a clock signal, leading to larger power dissipation, worse electromagnetic interference, and higher design cost. The latter also suffers from problems such as inflexibility of the system to frequency changes and high design costs. Embedded clock receivers that automatically adjust their data rates without using reference clock signals can overcome these problems. Several frequency acquisition schemes that can extract the frequency information from the input data without using an external reference clock signal have been proposed [1]–[3]. However, because of the limited frequency acquisition range, these schemes cannot be used in wide-range applications such as flat-panel display links. Wide-range clock and data recoveries (CDRs) for embedded clock receivers have been presented in [4]–[6]. However, CDRs in [4] and [5] suffer from large jitters in the lock state since they use edge-detection methods for phase adjustment. In addition, for CDRs in [4] and [6], it takes a long time to acquire the frequency because of their slow frequency-band selection schemes and frequency acquisition processes. Furthermore, CDRs in [5] and [6] require periodic predefined patterns, such as repeated comma patterns in 8B10B encoding, for their frequency acquisition processes, or special sync patterns, in addition to the encoding schemes for dc balancing and frequency information acquisition. These approaches can significantly reduce the data throughput of systems.